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21ic
12 年
基于FPGA的RS码译码器的设计
[导读]摘要:介绍了符合CCSDS标准的RS(255,223)码译码器的硬件实现结构。译码器采用8位并行时域译码算法,主要包括了修正后的无逆BM迭代译码算法,钱搜索算法和Forney算法。采用了三级流水线结构实现,减小了译码器的时延 摘要:介绍了符合CCSDS标准的RS(255 ...
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