Abstract: This study presents a method for generating synthesizable Verilog code for digital integrated circuits directly from natural-language specifications. The approach combines large language ...

Abstract: Hardware design automation faces challenges in generating high-quality Verilog code efficiently. This paper introduces VFlow, an automated framework that optimizes agentic workflows for ...

A collection of simple, real-world cybersecurity scripts for threat detection, network scanning, log analysis, and incident response. Built as part of my transition into cybersecurity, this repo ...