Design-Reuse

Synopsys' DesignWare DDR PHY Compiler Eases Integration of Memory Interface IP

MOUNTAIN VIEW, Calif., Jan. 26, 2011-- Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced the immediate ...
Design-Reuse

Fujitsu and Denali Software Collaborate to Develop DFI Compatible DDR PHY Macro

Hamamatsu City, Shizuoka, Japan -- Sept 19, 2007-- Fujitsu Limited and Denali Software, Inc. today announced their co-development of a DDR DRAM physical interface (DDR PHY) product compatible with the ...
EDN

Design tool yields DDR memory interface IP

The DDR PHY compiler is said to be the industry’s first DDR SDRAM design tool. It enables assembly of a complete, customized high-performance DDR PHY for ASICs, ASSPs, or SoC applications while ...
Electronic Design

Cadence and Denali Double-Team Advanced DDR-PHY Methodology

The combined resources of Cadence Design Systems and Denali Software have resulted in an advanced double-data-rate (DDR) PHY methodology based on Cadence’s Encounter digital IC design platform. The ...
EDN

Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards in a Single PHY

MOUNTAIN VIEW, Calif., April 7 /PRNewswire-FirstCall/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and ...
Business Wire

Faraday Delivers DDR/LPDDR Combo PHY IP Solutions on UMC’s 22ULP and 14FFC

HSINCHU, Taiwan--(BUSINESS WIRE)--Faraday Technology Corporation (TWSE: 3035), a leading ASIC design and IP provider, today announced the availability of its DDR/LPDDR combo PHY, supporting from 3 rd ...